In a typical 3D memory device, word lines are connected to the decoders disposed at the periphery region mainly by poly-silicon and silicide paths, which are not high-conductivity paths for signals. To improve the operational efficiency of the memory, it usually uses two X-decoders at two opposite sides of a memory array region. The two X-decoders accept the same signal and transfer the same signal to the array region simultaneously during the device operation. As such, the signal can be transferred through a shorter path, and the RC delay of word line signal is improved.
As the shrink of the size of memory devices, the two X-decoders method is harmful to the array efficiency. How to reduce the area of X-decodes by improving the RC delay of word line becomes important. One way is using metal word line process. However, this process is hard to be carried out especially for the vertical gate structure because of its process flow and yield control.